FIG. 1 illustrates a prior art memory interconnect system that includes a memory controller 10 and one or more memory modules 12 that communicate through a channel made up of point-to-point links. The channel has an outbound path that includes one or more outbound links 14, and an inbound path that includes one or more inbound links 16. Each module redrives signals from link to link on the outbound path and from link to link on the inbound path. Each module may also process any request sent by the memory controller. Each module may also be capable of selectively disabling any redrive features, for example, if the module detects that it is the outermost module, or in response to a command from the memory controller.
Each module includes one or more memory devices 18 arranged to transfer data to and/or from one or more of the paths. For example, a module may be arranged such that data from the outbound path is transferred to a memory device, and data from the memory device is transferred to the inbound path. One or more buffers may be disposed between one or more memory devices and one or more of the paths. The memory devices may be read only memory (ROM), dynamic random access memory (DRAM), flash memory, etc.
FIG. 2 illustrates a prior art memory module 12 that includes two redrive circuits 20 and 22 to receive signals on links 14A and 16A, and redrive the signals on links 14B and 16B, respectively. One or more memory devices 18 are arranged to transfer data to and/or from one or more of the redrive circuits.
If the module of FIG. 2 is used in a memory system such as that shown in FIG. 1, then redrive circuit 20 might be designated as an outbound redrive circuit and arranged to receive and redrive signals on an outbound path including links 14A and 14B, and the other redrive circuit 22 might be designated as an inbound redrive circuit and arranged to receive and redrive signals on an inbound path including links 16A and 16B. One or more memory devices 18 may be arranged so that data is transferred from the outbound redrive circuit 20 to the memory device(s) and from the memory device(s) to the inbound redrive circuit 22.
FIG. 3 illustrates another prior art memory module. The module 12 of FIG. 3 includes a memory buffer 24 having two redrive circuits 20 and 22 to receive signals on links 14A and 16A, and redrive the signals on links 14B and 16B, respectively. The memory buffer also includes a memory interface 26 arranged to transfer data to and from one or more memory devices 18.
If the module of FIG. 3 is used in a memory system such as that shown in FIG. 1, then redrive circuit 20 might be designated as an outbound redrive circuit and arranged to receive and redrive signals on an outbound path including links 14A and 14B, and the other redrive circuit 22 might be designated as an inbound redrive circuit and arranged to receive and redrive signals on an inbound path including links 16A and 16B.
FIG. 4 illustrates another prior art memory interconnect system with memory modules 12 and memory buffers 24. The modules are populated with memory devices 18, for example, commodity-type DRAM such as Double Data Rate II (DDR2) DRAM and arranged in a dual inline memory module (DIMM) configuration. A memory buffer 24 on each module isolates the memory devices from a channel that interfaces the modules to the memory controller 10, which is also referred to as a host. The channel is wired in a point-to-point arrangement with an outbound path that includes outbound links 14, and an inbound path that includes inbound links 16. The links may be implemented with parallel bit lanes using low-voltage differential signals.
In the system of FIG. 4, no additional signal lines are used for functions such as command, reset, initialization, and the like. Instead, these functions are encoded directly in the data sent over the channel. Memory systems implementing these features are being deployed under the name Fully Buffered DIMM or FBDIMM.
The host may initiate data transfers by sending packets to the innermost module on the outbound path. The innermost module receives and redrives the data to the next module on the outbound path. Each module receives and redrives the outbound data until it reaches the outermost module. Although the outermost module could attempt to redrive the data to a “nonexistent” outbound link, each module may be capable of detecting (or being instructed) that it is the outermost module and disabling any redrive circuitry to reduce unnecessary power consumption, noise, etc. Each module processes every data packet it receives, regardless of whether the packet is intended for the module, or destined for another module further down the outbound path. Data transfers in the direction of the host, i.e., inbound, are initiated by the module that contains the requested data. Each module between the host and module that contains the requested data receives and redrives inbound data along the inbound path until reaches the host.